A conventional microprocessor, such as INTEL'S P6, has a predetermined configuration (resulting from design trade-offs) that allows certain types of application programs to run faster than other types. For example, INTEL'S P6 is optimized for 32-bit software, i.e. runs application programs having 32-bit programming model faster than application programs having 16-bit programming model.
Specifically, an article "P6 stirs up software issues", by Alexander Wolfe, Electronic Engineering Times, Oct. 30, 1995, page 22 states: "a 133-MHz P6 running Windows 3.1 runs 10 to 20% slower than a Pentium". The article also cites an INTEL warning that "programs that intermix . . . use of 8-, 16- and 32-bit registers can result in partial pipeline stalls, which slow performance."
According to Wolfe, "Intel is providing special optimizing compilers and a software performance aide called the Visualized Tuning Tool (V Tune)." However, such tools fail to improve the performance of application programs (such as 16-bit code) that predate the P6. Therefore, to use INTEL's P6 a user must discard such preexisting software and buy a new generation of 32-bit software at a considerable expense.
Conventional microprocessors, such as INTEL's PENTIUM.TM. have one or more on-chip caches with "modes", such as a "cache disabled" (CD) mode and a "not write thru" (NW) mode. The PENTIUM's modes are described in "Pentium.TM. Processor User's Manual" (see in particular Volume 1, Chapter 3) available from Intel Corporation, Literature Sales, PO Box 7641, Mt. Prospect, Ill. 60056-7641 that is incorporated by reference herein in its entirety. For example, setting a bit CD to 0 in register CR0 of the PENTIUM.TM., results in disabling a cache in the PENTIUM.TM.(see Table 3-2 of the above-incorporated manual). Moreover, Intel states that "the cache must be flushed after being disabled . . . ".